Jennic has a long track record of delivering 1st time right chip designs for Mixed mode, digital and RF silicon systems. Established in 1996, it leverages its design services capabilities together with an extensive portfolio of IP in order to reduce project risk and timescales. Design capabilities cover the whole range from analogue / RF systems to complex digital/analogue systems and software. Typically, a project starts from specification and delivers verified GDSII for the target process technology. Example projects have included an SPI4.2 to quad SPI3 bridge device on 0.18um CMOS, a GSM/EDGE receiver chain on a SiGe BiCMOS process and a single chip device for IEEE802.15.4 low power wireless applications. A range of high end simulation tools are used, including Cadence Analog artist and Diva, Mentor ADMS, Modelsim etc, Agilent ADS for analogue / digital design. For physical implementation, or SoC services, it uses Synopsys, and Mentor tools to deliver verified GDSII complete with test insertion.

Jennic specializes in delivering chip level designs to customer specifications and timescales, using its own IP where possible to accelerate the process.

Prime:		Design
Subsidiary:		IP
Employees:		40

Broadband and Wireless Communications and ASIC markets

PC Based:	Yes
Other:	Unix based tools
Details:	A full suite of tools supporting analogue, RF and digital ASIC design, including Cadence Analog Artist, Diva Mentor Calibre, ADMS, Modelsim, DFTAdvisor etc, Agilent ADS, Synopsys DC expert and others.