GarField Microelectronics Ltd is primarily involved in ASIC and FPGA design. At the start of a project we will agree a specification with the customer, this may be generated by either party. We support all levels of technology using a wide range of design tools. GarField designers will assist in any stage of the design process from initial specification through to layout, and have experience in well over 300 designs. Our preferred design methodology involves the use of VHDL throughout the process for simulation, test and synthesis. We have extensive experience in design for test (ATPG, JTAG, scan) and have 100% success rate on turnkey designs. GarField's design methodology and links to key silicon vendors allow a low cost conversion route from FPGA to ASIC, and a re-targeting service from ASIC to ASIC. This is especially useful to customers experiencing supply problems with existing ASIC sources. GarField has developed several standard products in association with its customers, and offers a marketing and sales service to support these. Although "silicon vendor independent", we have strong links with several silicon vendors and will support the customers requirements by holding buffer stocks enabling a flexible and reliable delivery programme.

Prime:		Design / Consultancy / Distribution / Training
Subsidiary:		Test
Employees:		10-50

	PLD		FPGA		Masked ASIC
	Microcontroller		Other

Data processing, communications, industrial, military, automotive, consumer.

PC Based:	YES	Other:	YES
Details:	Viewlogic, Compass, Synopsys, ModelTech, Exemplar, Cadence, Intergraph, Mentor, VHDL, Verilog.