Synopsys' goal is to increase dramatically design productivity by providing new generations of software tools for EDA. Synopsys is the leader in top level EDA tools - synthesis simulation of design re-use - the components of HLDA and the tools our customers use to quickly design new products.

Synthesis is the enabling technology of HLD and our unrivalled synthesis product line is the company's 'flagship' - our synthesis tools support FPGA, mainstream logic and higher complexity and performance designs.

Synopsys provides design for test solutions that address the test strategies for a variety of design environments. Test compiler offers constraint based partial scan and full scan support. For verification, Synopsys provides increased simulation speed and productivity, covering all phases of the design process and tightly linked with the synthesis environment for maximum design productivity. The Synopsys simulator is the first to achieve ASIC sign-off. Sign-off commitments assure both the ASIC Supplier and our customer that the simulated results are correct.

Prime:		EDA Software sales & consultancy
Subsidiary:		Distribution / Production / Training
Employees:		>50

	High Level Capture / Simulation		Low Level (Schematic) Capture / Simulation		Synthesis
	Test		Physical Design		Design Verification

	High Level Design Capture / Simulation		PCB Design		Thermal Design / Simulation
	EMC		Test

Mentor, Cadence, Avanti

LSI, Toshiba, Fujitsu, NEC, TI, and many others

Workstation SUN, HP