Sabre Advanced Microelectronics Ltd. Support and assist customers to design / develop in both Verilog and VHDL formats. From initial design we can provide a "quick turn" solution in FPGA and then directly migrate to ASIC when circumstances change.The "low cost" FPGA tools cover schematic capture, Synthesis , simulation in both Verilog & VHDL and place & route tools for layout. These "low cost" tools can be "upgraded" at a later stage to cover ASIC design. Tools include "timing driven placement" , "static timing analysis" & 100% place and route with pre-determined (fixed) pin/pad allocation.
Prime:
  Sales & Tech support on FPGA & ASIC Designs
Subsidiary:
  
Employees:
   <50


High Level Capture / Simulation

Low Level (Schematic) Capture / Simulation

Synthesis

Test

Physical Design

Design Verification


High Level Design Capture / Simulation

PCB Design

Thermal Design / Simulation

EMC

Other


Mentor, Cadence, Model technology, Synopsys, Viewlogic, Synplicity, Exemplar, Synario, Aldec, Simucad


IBM PC or Compatible, Workstation


www.sabreadv.com


sales@sabreadv.com
 


Address:
Sussex House,
The Pines Business Park, Broad Street,
Guildford,
Surrey.
GU3 3BH
tel:
01483 535444
fax:
 01483 535888
Sales:
 Paul Crossley

Technical Contact:
Gary French
 





PLD
FPGA
MPGA
CBIC
ANALOG
MIXED SIG.
FULL CUST.
PC-BASED CAD (EDA) TOOLS
-
-
-
-
-
-
-
Design Styles Supported
Y
Y
Y
Y
Y
Y
Y
Entry Level Costs
P.O.A
P.O.A
P.O.A
P.O.A
P.O.A
P.O.A
P.O.A
Annual Maintenance Charges
15%
15%
15%
15%
15%
15%
15%
Workable Minimum Configuration
Windows 95 / 98 or NT
WORKSTATION CAD (EDA) TOOLS
-
-
-
-
-
-
-
Design Styles Supported
Y
Y
Y
Y
Y
Y
Y
Entry Level Costs
P.O.A
P.O.A
P.O.A
P.O.A
P.O.A
P.O.A
P.O.A
Annual Maintenance Charges
15%
15%
15%
15%
15%
15%
15%
Workable Minimum Configuration
-

PLD = Programmable Device, FPGA = Field Programmable Gate Array
MPGA = Mask Programmable Gate Array, CBIC = Cell Based Integrated Circuit