Esperan is a training and consultancy company offering vendor independent methodology training to the electronic design community. Our courses are divided into three main areas that encompass all aspects of completing a project successfully:

IP Creation: successful design, synthesis and verification using VHDL or Verilog.
Design Realisation: ASIC design issues including flows, testability, low power design. FPGA design covering all aspects of designing with Xilinx and Altera leading edge PCB design issues, signal integrity and EMI.
Design Environment: Controlling the design environment using Unix, TCL and PERL.

Courses are run regularly throughout Europe and can easily be customised to suit your particular requirements. Our presenters are drawn from a wide range of design consultants who have deep, up-to-the minute knowledge. They work closely with all major EDA software tool vendors and are able to offer training and advice on each customers chosen combination of tools.

Esperan also offers MasterClass, an interactive, multimedia VHDL or Verilog tutorial aimed at the PC based FPGA and PLD designer.

Prime:		Training
Subsidiary:
Employees:		<10

	High Level Capture / Simulation		Low Level (Schematic) Capture / Simulation		Synthesis
	Test		Physical Design		Design Verification

	High Level Design Capture / Simulation		PCB Design		Thermal Design / Simulation
	EMC		Other - Masked ASIC

Model Technology, Exemplar, Synario, Viewlogic, Altera, Actel, Cypress, Synplicity, Veribest, Mentor, Synopsys, Cadence, Xilinx.

IBM PC or Compatible