Digital Techniques offers Intelligent Logic - Speed / technology independent ASIC design, functionally checked in logic synthesis (chip will reproduce tests). Self-teaching package with GUI reference to designs including combinational and finite state machine, fixed and floating point arithmetic. EDIF netlist providing link to third party software. Automatic behavioural level documentation (no language to learn). Simplified testing procedures. Reliable circuits with continual testing (safety critical application) / low power consumption/low noise. Higher levels of integration. Micro design as alternative engine (+ space) to microprocessor (speed and chip space advantages). No clocks / no timing problems.

Prime:		Tool Origination / Training
Subsidiary:
Employees:		<10

	High Level Capture / Simulation		Low Level (Schematic) Capture / Simulation		Synthesis
	Test		Physical Design		Design Verification

IBM PC or Compatible