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Agilent Technologies EEsof's Advanced Design System is a new EDA solution developed specifically to simulate that entire communications signal path. This unique solution, available for both PC ad UNIX platforms, integrates Agilent EEsof's proven DSP simulator with RF and analog simulators into a single, flexible design environment. The result is a software solution that takes your DSP design from accurate behavioural-level system simulation, incorporating non-linear RF effects, all the way down to RTL or component-level circuit design, all within one user interface and one database. The system level modelling, design and optimisation capabilities in Agilent Advanced Design System will help you conquer the DSP ASIC design challenge.
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PLD
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FPGA
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MPGA
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CBIC
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ANALOG
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MIXED
SIG.
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FULL
CUST.
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| PC-BASED CAD (EDA) TOOLS |
-
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-
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-
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-
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-
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-
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-
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| Design Styles Supported |
Y
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Y
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Y
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Y
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Y
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Y
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Y
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| Entry Level Costs |
P.O.A
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P.O.A
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P.O.A
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P.O.A
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P.O.A
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P.O.A
|
P.O.A
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| Annual Maintenance Charges |
12%
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12%
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12%
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12%
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12%
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12%
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12%
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| Workable Minimum Configuration |
Windows
95 / 98 / NT
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| WORKSTATION CAD (EDA) TOOLS |
-
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-
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-
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-
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-
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-
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-
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| Design Styles Supported |
Y
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Y
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Y
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Y
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Y
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Y
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Y
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| Entry Level Costs |
P.O.A
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P.O.A
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P.O.A
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P.O.A
|
P.O.A
|
P.O.A
|
P.O.A
|
| Annual Maintenance Charges |
12%
|
12%
|
12%
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12%
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12%
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12%
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12%
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| Workable Minimum Configuration |
HPUX,
Solaris, SunOS, AIX
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PLD =
Programmable Device, FPGA = Field Programmable Gate Array
MPGA = Mask Programmable Gate Array, CBIC
= Cell Based Integrated Circuit