The Altera MAX+PLUS
II development tool is the leading development environment for high density
programmable logic, supporting high level design description from all
leading EDA tools, or directly through VHDL, Verilog and Schematic Description.
Multi-device partitioning is supported with timing driven synthesis and
fast compile timers which provide a high productivity design environment.
Altera's fourth generation development system, QuartusTM,
allows designers to process multi-million gate designs
offering seamless integration with the major synthesis and verification
tools to support existing design flows. Quartus also offers a host of
new advanced features such as "on-chip" real-time logic analysis
and debugging support, available through the unique SignalTapTM
feature, and Web based support for easy updates and on-line
help.
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Prime:
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Subsidiary:
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Employees:
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>50 |
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High Level Capture / Simulation |
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Low Level (Schematic) Capture / Simulation |
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Synthesis |
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Test |
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Physical Design |
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Design Verification |
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High Level Design Capture / Simulation |
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PCB Design |
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Thermal Design / Simulation |
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EMC |
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Other | ||
All leading EDA tools.
All leading EDA tools.
IBM PC or Compatible,
Workstation Sun SPARCstation,HP9000 Series 700, IBM RS6000
