The Actel designer and design advantage systems are high-productivity, computer-aided engineering environments for the Actel family of field programmable gate arrays (FPGAs). These design tools are fully automatic and with version 3.0, provide fully deterministic timing. Features include : design mapping, device place and route, VHDL synthesis, macro generation, timing analysis and programming.


Prime:
  Production / Distribution / Training
Subsidiary:
 
Employees:
  <380


High Level Capture / Simulation

Low Level (Schematic) Capture / Simulation

Synthesis

Test

Physical Design

Design Verification


Actel Designer system


Viewlogic, Cadence, Mentor, Orcad, Suziecad, Synopsis, 1st, Veribest, Synplicity, Synopsys.


MX/SX/SXA, ACTI, ACT2, ACT3,1200XL, 3200DX


IBM PC or Compatible, Workstation SUN Solaris


www.actel.com


sharon.blades@actel.com

 


Address:
Daneshill House,
Lutyens Close,
Basingstoke,
Hampshire.
RG24 8AG
tel:
01256 305600
fax:
01256 355420
Sales:
Sharon Blades

Technical Contact: Joe Wells

 





 
PLD
FPGA
MPGA
CBIC
ANALOG
MIXED SIG.
FULL CUST.
PC-BASED CAD (EDA) TOOLS
-
-
-
-
-
-
-
Design Styles Supported
Y
Y
Y
-
-
-
-
Entry Level Costs
£0
£0
£0
-
-
-
-
Annual Maintenance Charges
-
$995
-
-
-
-
-
Workable Minimum Configuration
IBM PC compatible, 486DX with VGA 16Mb RAM, 150Mb disk
WORKSTATION CAD (EDA) TOOLS
-
-
-
-
-
-
-
Design Styles Supported
-
Y
-
-
-
-
-
Entry Level Costs
-
FOC
-
-
-
-
-
Annual Maintenance Charges
-
$995
-
-
-
-
-
Workable Minimum Configuration
Sun 4 compatible, Sun OS / Solaris, HP700 Series

PLD = Programmable Device, FPGA = Field Programmable Gate Array
MPGA = Mask Programmable Gate Array,
CBIC = Cell Based Integrated Circuit